The present invention relates to an integrated circuit of the CMOS or BICMOS type, comprising a substrate with sub-circuits provided with a number of terminals, including a substrate terminal or earthing point, a Vcc power supply terminal, an input point and an output point, wherein at least one of the Vcc power supply terminal, the input point or the output point is connected via an overvoltage protection circuit to the substrate terminal or earthing point, wherein the overvoltage protection circuit comprises means with diode action formed in the substrate between the relevant terminal and the substrate terminal or earthing point.
Integrated circuits have to be protected from damage resulting from Electrostatic Discharge (ESD), which is characterized by pulses of high voltage (several kVs) of short duration (several ns) and an amperage of a few amperes. Sources of ESD are for instance the human body and electrical fields generated by machines.
The sensitivity to electrostatic discharge increases with the ever further miniaturization of integrated circuits.
An overvoltage protection circuit for protecting an integrated circuit from electrostatic discharge (ESD)is known wherein a parallel circuit is applied of on the one hand a diode in serial combination with a resistor and on the other an NMOS transistor, the gate of which is connected to the node between the diode and the resistor. A drawback of the known overvoltage protection circuit is that it takes up a relatively large amount of space on the substrate. A further drawback of the known protection circuit is that a diode of the avalanche type is employed, i.e. that diode breakdown substantially occurs as a result of the avalanche effect. Although such a diode can have a relatively high disruptive voltage, for instance in the order of magnitude of 10 V, the switching speed is relatively low, which is disadvantageous for receiving rapid pulses, and the serial resistance is relatively high, which results in a relatively large voltage drop in the case of ESD pulses. Both factors therefore have an adverse effect on the protective capacity of the protection circuit.
Instead of a diode of the avalanche type a diode of the real Zener type can be applied, i.e. a diode in which diode breakdown occurs substantially as a result of the so-called Zener effect. Such diodes have a higher switching circuit speed as well as a lower serial resistance. The drawback of Zener diodes is that operating voltage is low, about 5 V, which limits applicability to protecting circuits with a relatively small voltage difference between the relevant terminals.
It is an object of the present invention to provide an integrated circuit of the above described type which is provided with an overvoltage protection circuit in which the above stated drawbacks are obviated.
According to a first aspect of the invention an integrated circuit is provided comprising a substrate with sub-circuits provided with a number of terminals, including a substrate terminal or earthing point, a Vcc power supply terminal, an input point and an output point, wherein at least one of the Vcc power supply terminal, the input point or the output point is connected via an overvoltage protection circuit to the substrate terminal or earthing point, wherein the overvoltage protection circuit comprises means with diode action formed in the substrate between the relevant terminal and the substrate terminal or earthing point, wherein the means comprise two or more diode elements of the Zener type connected in series, and the substrate of a first conductivity type is provided with a well of a second, opposed conductivity type formed in the substrate, and wherein a first diode element is provided in the substrate of the first conductivity type and is formed by a first pn junction between two surface areas of opposed conductivity types arranged in the substrate and at least one second diode element is provided in the well of the second conductivity type and is formed by a second pn junction between two surface areas of opposed conductivity types arranged in the well, and wherein the well insulates at least the second diode element from the first diode element. By placing two or more Zener diodes in series a very rapid protection from electrostatic discharge (ESD) is provided which can be applied generally to integrated circuits of random operating voltage.
According to a preferred embodiment the anode part of the first diode element is electrically connected to the substrate terminal or earthing point and the cathode part is electrically connected to the anode part of the second diode element, and the cathode part of the second diode element is electrically connected to the anode part of a further diode element or to the relevant terminal.
According to a further preferred embodiment the junctions are formed by p+ respectively n+ surface areas, wherein an n+ surface area of the p-n junction is formed in a p+ surface area and the n+ surface area of the p-n junction of the second diode element and the well are mutually separated by the p+ surface area. In these embodiments a surface area of conductivity type corresponding with the conductivity type of the well is arranged in the well to bring the well to an appropriate voltage. In another preferred embodiment the n+ surface area and the p+ surface area of a diode element are positioned immediately adjacently of each other. It is also possible to form a p+ surface area inside the n+ surface area, this such that the p+ surface area interrupts the interface with the substrate.
Although in the foregoing the substrate is manufactured from P-type material and the well from N-type material, the invention is equally applicable to a substrate of the N-type and a well of the P-type. The invention can also be applied in a so-called twin-well process.
According to another aspect of the invention a method is provided for manufacturing a protection circuit of the above described type, wherein the method comprises of:
arranging a well of second conductivity type in a substrate of a first conductivity type by diffusion;
arranging a highly doped surface area of the second conductivity type in the well by diffusion;
arranging a highly doped surface area of the second conductivity type in the substrate by diffusion;
arranging highly doped surface areas of the first conductivity type in the highly doped surface areas of the second conductivity type by diffusion.